1. Field of the Invention
The present invention relates to a single slope AD converter circuit (Single Slope Analog-To-Digital Converter Circuit, hereinafter referred to as an SSADC, and AD converter circuit is referred to as an ADC), and in particular, relates to a signal AD converter circuit provided with a comparator that compares a ramp voltage with an analog input voltage.
2. Description of the Related Art
In order to achieve ultralow power consumption of LSI (Large Scale Integration), a sub-threshold LSI that utilizes a sub-threshold region operation of MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor, hereinafter referred to as a MOS transistor) attracts attention. However, since this designing method is in the initial stage of development, establishment of a designing technique of an ultralow power consumption circuit is strongly demanded. Up to now, various researches have been made to achieve an ultralow power LSI.
The AD converter circuit is a circuit block that converts an analog signal of a sensor signal, an audio signal or the like into a digital signal. The SSADC is also called PPM (Pulse Position Modulation) ADC (See, for example, the Non-Patent Document 1 and the Patent Documents 1 and 2), and used as a low-speed ADC.
FIG. 1 is a circuit diagram showing a configuration of a prior art SSADC. Referring to FIG. 1, the prior art SSADC is configured to include a current source circuit 1, a sample hold circuit 2, a p-channel MOS transistor Q1, a capacitor C, a comparator 3, a switch SW1 that is turned on in response to an inverted reset signal /RST, a switch SW2 that is turned on in response to a reset signal RST, and a counter 4 that performs counting of a clock from a clock generator 8, and can be provided by a simple circuit block. In the present specification, the slash mark/before the signal symbol represents a low active signal. It is noted that VDDH is a power voltage of, for example, 1.8 V for an analog circuit, and VDDL is a power voltage of, for example, 0.4 V for use in a digital circuit. Moreover, there is sometimes a case where a reference current is externally supplied instead of the reference current source circuit 1 (See, for example, the Non-Patent Document 1).
FIG. 2 is a timing chart of signals showing an operation of the SSADC of FIG. 1. Referring to FIG. 2, by turning on and off the switch SW2 in synchronization with the fall of the reset signal RST and thereafter turning on the switch SW 1 to supply a constant reference current IREF to the capacitor C, a ramp voltage VRMP, whose voltage rises with a predetermined slope as the time elapses, is generated. Then, the comparator 3 compares a voltage obtained by sampling and holding an analog input voltage (hereinafter, referred to as an input voltage) VIN by the sample hold circuit 2 with the generated ramp voltage VRMP. In this case, by measuring time to when the ramp voltage VRMP and the input voltage VIN become equal to each other by clock counting by the counter 4, the input voltage VIN is converted into a digital value DVIN. The outputted digital value DVIN is expressed by the following equation:
                              D          VIN                =                                            CV              IN                                      I              REF                                ⁢                                    f              CLK                        .                                              (        1        )            
In this case, fCLK is a frequency of the clock. It can be understood from the Equation (1) that the digital value DVIN is outputted in accordance with the input voltage VIN.
The digital value shown in the Equation (1) is satisfied only in an ideal case. In practice, the value receives influences from non-ideal factors of the delay time of the comparator 3 and PVT variations (indicating variations in manufacturing process, voltage and temperature) and so on. When these non-ideal factors exist, the digital value DVIN is expressed by the following equation:
                              D          VIN                =                              (                                                                                (                                          C                      +                                              Δ                        ⁢                                                                                                  ⁢                        C                                                              )                                    ⁢                                      (                                                                  V                        IN                                            +                                              V                        OFF                                                              )                                                                                        I                    REF                                    +                                      Δ                    ⁢                                                                                  ⁢                                          I                      REF                                                                                  +                              τ                CMP                                      )                    ⁢                                    (                                                f                  CLK                                +                                  Δ                  ⁢                                                                          ⁢                                      f                    CLK                                                              )                        .                                              (        2        )            
In this case, ΔC is the variation of the capacitor C, VOFF is the offset voltage of the comparator 3, ΔIREF is the variation of a reference current IREF, τCMP is the delay time of the comparator 3, and ΔfCLK is the variation of the clock frequency fCLK.
Prior Art Documents related to the present invention are as follows: